Filter
Top Products
44 www.xilinx.com Ethernet AVB Endpoint User Guide
UG492 July 23, 2010
Chapter 5: Core Architecture
Precise Timing Protocol Blocks
The various hardware Precise Timing Protocol (PTP) blocks within the core provide the
dedicated hardware to implement the IEEE P802.1AS specification. However, the full
functionality is only achieved using a combination of these hardware blocks coupled with
functions provided by the “Software Drivers” (run on an embedded processor).
Consequently the following hardware block descriptions also give some insight into the
software driver functionality.
Note:
The following definitions provide only a simplistic concept of PTP protocol operation. For
detailed information about the PTP protocol, see the IEEE P802.1AS specification.
Tx PTP Packet Buffers
The PTP packet buffer contains pre-initialized templates for seven different PTP packets
defined by the P802.1AS specification. The buffer contents are read/writable through the
PLB and a separate configuration register within the core requests to the Tx Arbiter which
of these seven packets is to be transmitted. A dedicated interrupt signal will be generated
by the core whenever a PTP packet has been transmitted.
The software drivers provided with the core, using the PLB and dedicated interrupts, will
use this interface to periodically update specific fields within the PTP packets, and request
transmission of these packets. See Chapter 9, “Precise Timing Protocol Packet Buffers” for
further information.
Tx Time Stamp
Whenever a PTP packet is transmitted, a sample of the current nanosecond value of the
local RTC is taken. This timestamp value is written into a dedicated field within the Tx PTP
Packet Buffer, where it is accessible along side the content of the PTP frame that was just
transmitted. By the time the Tx PTP buffer raises its dedicated interrupt, this time stamp is
available for the microprocessor to read. This sampling of the RTC is performed in
hardware for accuracy. See Chapter 9, “Precise Timing Protocol Packet Buffers” for further
information.
Rx PTP Packet Buffers
Received PTP Packets will be written to the Rx PTP Packet Buffer by the Rx Splitter. This
buffer is capable of storing up to 16 separate PTP frames. Whenever a PTP packet is
received, a dedicated interrupt will be generated. The contents of the stored packets can be
read via the PLB. The oldest stored frame will always be overwritten by a new frame
reception and so a configuration register within the core will contain a pointer to the most
recently stored packet.
The software drivers provided with the core, using the PLB and dedicated interrupt, will
use this interface to decode, and then act on, the received PTP packet information. See
Chapter 9, “Precise Timing Protocol Packet Buffers” for further information.
Rx Time Stamp
When a PTP packet is received, a sample of the current nanosecond value of the RTC is
taken. This timestamp value is written into a dedicated field within the Rx PTP Packet
Buffer, where it is accessible along side the PTP frame that was just received. By the time
the Rx PTP buffer raises its dedicated interrupt, this time stamp is available for the
microprocessor to read. This sampling of the RTC is performed in hardware for accuracy.
See Chapter 9, “Precise Timing Protocol Packet Buffers” for further information.