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Power Management
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
8-4 Freescale Semiconductor
8.2.1.1 Peripheral Power Management Register Low (PPMRL)
IPSBAR
Offset: 0x0018 (PPMRL)
Access: read/write
31 30 29 28 27 26 25 24
R 0 0 0 0 0 000
W
Reset 0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
R0 0 0 0 0 0
CDINTC0 CDTMR3
W
Reset 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
R
CDTMR2 CDTMR1 CDTMR0
00
CDQSPI CDI2C
0
W
Reset 0 0 0 0 0 0 0 0
76 5 43210
R
CDUART2 CDUART1 CDUART0 CDDMA
1 0
CDG
0
W
Reset 0 0 0 0 1 000
Figure 8-2. Peripheral Power Management Register Low (PPMRL)
Table 8-3. PPMRL Field Descriptions
Field Description
31–18 Reserved, should be cleared.
17
CDINTC0
Disable clock to the INTC0 module.
0 INTC0 module clock is enabled
1 INTC0 module clock is disabled
16
CDTMR3
Disable clock to the DTIM3 module.
0 TMR3 module clock is enabled
1 TMR3 module clock is disabled
15
CDTMR2
Disable clock to the DTIM2 module.
0 TMR2 module clock is enabled
1 TMR2 module clock is disabled
14
CDTMR1
Disable clock to the DTIM1 module.
0 TMR1 module clock is enabled
1 TMR1 module clock is disabled
13
CDTMR0
Disable clock to the DTIM0 module.
0 TMR0 module clock is enabled
1 TMR0 module clock is disabled
12–11 Reserved, should be cleared.