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IEEE 1149.1 Test Access Port (JTAG)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
29-6 Freescale Semiconductor
The boundary scan register contains bits for bonded-out and non bonded-out signals, excluding JTAG
signals, analog signals, power supplies, compliance enable pins, and clock signals.
29.4 Functional Description
29.4.1 JTAG Module
The JTAG module consists of a TAP controller state machine, which is responsible for generating all
control signals that execute the JTAG instructions and read/write data registers.
29.4.2 TAP Controller
The TAP controller is a state machine that changes state based on the sequence of logical values on the
TMS pin. Figure 29-4 shows the machine’s states. The value shown next to each state is the value of the
TMS signal sampled on the rising edge of the TCLK signal.
Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As
Figure 29-4 shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also
causes the state machine to enter the test-logic-reset state, whatever the initial state.