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MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
24-10 Freescale Semiconductor
Table 24-7 describes UCRn fields and commands. Examples in Section 24.4.2, “Transmitter and Receiver
Operating Modes,” show how these commands are used.
IPSBAR
Offset:
0x00_0208 (UCR0)
0x00_0248 (UCR1)
0x00_0288 (UCR2)
Access: User write-only
76543210
R
W 0 MISC TC RC
Reset:00000000
Figure 24-7. UART Command Registers (UCRn)
Table 24-7. UCRn Field Descriptions
Field Description
7 Reserved, must be cleared.
6–4
MISC
MISC Field (this field selects a single command)
Command Description
000 NO COMMAND —
001 RESET MODE
REGISTER POINTER
Causes the mode register pointer to point to UMR1n.
010 RESET RECEIVER Immediately disables the receiver, clears USRn[FFULL,RXRDY], and reinitializes
the receiver FIFO pointer. No other registers are altered. Because it places the
receiver in a known state, use this command instead of
RECEIVER DISABLE when
reconfiguring the receiver.
011 RESET
TRANSMITTER
Immediately disables the transmitter and clears USRn[TXEMP,TXRDY]. No other
registers are altered. Because it places the transmitter in a known state, use this
command instead of
TRANSMITTER DISABLE when reconfiguring the transmitter.
100
RESET ERROR
STATUS
Clears USRn[RB,FE,PE,OE]. Also used in block mode to clear all error bits after
a data block is received.
101 RESET BREAK–
CHANGE INTERRUPT
Clears the delta break bit, UISRn[DB].
110
START BREAK Forces UTXDn low. If the transmitter is empty, break may be delayed up to one bit
time. If the transmitter is active, break starts when character transmission
completes. Break is delayed until any character in the transmitter shift register is
sent. Any character in the transmitter holding register is sent after the break.
Transmitter must be enabled for the command to be accepted. This command
ignores the state of UCTS
n.
111 STOP BREAK Causes UTXDn to go high (mark) within two bit times. Any characters in the
transmit buffer are sent.