Filter
Top Products
Power Management
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 8-15
8.4.2.15 Programmable Interrupt Timers (PIT0–PIT1)
In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases
operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the
stopped value. It is the responsibility of software to avoid erroneous operation.
When not stopped, the PIT may generate an interrupt to exit the low-power modes.
8.4.2.16 PWM Module
The PWM module is user programmable as to how it behaves when the device enters wait mode
(PWMCTL[PSWAI]) and doze mode (PWMCTL[PFRZ]). If either of these bits are set, the PWM input
clock to the prescaler is disabled during the respective low-power mode.
In stop mode the input clock is disabled and PWM generation is halted.
8.4.2.17 BDM
Entering halt mode via the BDM port (by asserting the external BKPT pin) causes the CPU to exit any
low-power mode.
8.4.2.18 JTAG
The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected
by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power mode.
Toggling TCLK during any low-power mode increases the system current consumption.
8.4.3 Summary of Peripheral State During Low-Power Modes
The functionality of each of the peripherals and CPU during the various low-power modes is summarized
in Table 8-10. The status of each peripheral during a given mode refers to the condition the peripheral
automatically assumes when the STOP instruction is executed and the LPCR[LPMD] field is set for the
particular low-power mode. Individual peripherals may be disabled by programming its dedicated control
bits. The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the
CPU into run mode.
Table 8-10. CPU and Peripherals in Low-Power Modes
Module
Peripheral Status
1
/ Wakeup Capability
Wait Mode Doze Mode Stop Mode
CPU Stopped No Stopped No Stopped No
SRAM Stopped No Stopped No Stopped No
Flash Stopped No Stopped No Stopped No
System Control Module Enabled Yes
3
Enabled Yes
3
Stopped No
DMA Controller Enabled Yes Enabled Yes Stopped No
UART0, UART1 and UART2 Enabled Yes
2
Enabled Yes
2
Stopped No