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Reset Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
10-4 Freescale Semiconductor
10.5.2 Reset Status Register (RSR)
The RSR contains a status bit for every reset source. When reset is entered, the cause of the reset condition
is latched, along with a value of 0 for the other reset sources that were not pending at the time of the reset
condition. These values are then reflected in RSR. One or more status bits may be set at the same time.
The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset
condition.
RSR can be read at any time. Writing to RSR has no effect.
3
LVDIE
LVD interrupt enable. Controls the LVD interrupt if LVDE is set. This bit has no effect if the LVDE bit is a logic 0.
1 LVD interrupt enabled
0 LVD interrupt disabled
2
LVDRE
LVD reset enable. Controls the LVD reset if LVDE is set. This bit has no effect if the LVDE bit is a logic 0. LVD
reset has priority over LVD interrupt, if both are enabled.
1 LVD reset enabled
0 LVD reset disabled
1
—
Reserved, should be cleared.
0
LVDE
Controls whether the LVD is enabled.
1 LVD is enabled
0LVD is disabled
IPSBAR
Offset:
0x11_0001 (RSR) Access: User read-only
76543210
R WDR_ASY
NC
LVD SOFT 0 POR EXT LOC LOL
W
Reset: Reset Dependent
Figure 10-3. Reset Status Register (RSR)
Table 10-4. RSR Field Descriptions
Field Description
7
WDR_ASYN
C
Backup watchdog timer reset flag. This bit indicates whether the last reset was caused by a watchdog timer
timeout.
1 Last reset was caused by a backup watchdog timer timeout
0 Last reset was not caused by a backup watchdog timer timeout
6
LVD
Low voltage detect. Indicates that the last reset state was caused by an LVD reset.
1 Last reset state was caused by an LVD reset
0 Last reset state was not caused by an LVD reset
Table 10-3. RCR Field Descriptions (continued)
Field Description