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General Purpose Timer Module (GPT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
21-8 Freescale Semiconductor
21.6.6 GPT System Control Register 1 (GPTSCR1)
Table 21-8. GPTCNT Field Descriptions
Field Description
15–0
CNTR
Read-only field that provides the current count of the timer counter. To ensure coherent reading of the timer counter,
such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word
(16-bit) accesses be used.
A write to GPTCNT may have an extra cycle on the first count because the write is not synchronized with the
prescaler clock. The write occurs at least one cycle before the synchronization of the prescaler clock.
These bits are read anytime. They should be written to only in test (special) mode; writing to them has no effect in
normal modes.
IPSBAR
Offset: 0x1A_0006 (GPTSCR1)
Access: Supervisor read/write
76543210
R
GPTEN
0
TFFCA
0 0 0 0
W
Reset:00000000
Figure 21-7. GPT System Control Register 1 (GPTSCR1)
Table 21-9. GPTSCR1 Field Descriptions
Field Description
7
GPTEN
Enables the general purpose timer. When the timer is disabled, only the registers are accessible. Clearing GPTEN
reduces power consumption. These bits are read anytime, write anytime.
1 GPT enabled
0 GPT and GPT counter disabled
6–5 Reserved, should be cleared.
4
TFFCA
Timer fast flag clear all. Enables fast clearing of the main timer interrupt flag registers (GPTFLG1 and GPTFLG2)
and the PA flag register (GPTPAFLG). TFFCA eliminates the software overhead of a separate clear sequence. See
Figure 21-8.
When TFFCA is set:
• An input capture read or a write to an output compare channel clears the corresponding channel flag, CxF.
• Any access of the GPT count registers (GPTCNTH/L) clears the TOF flag.
• Any access of the PA counter registers (GPTPACNT) clears the PAOVF and PAIF flags in GPTPAFLG.
Writing logic 1s to the flags clears them only when TFFCA is clear.
1 Fast flag clearing
0 Normal flag clearing
3–0 Reserved, should be cleared.