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EM78P259N/260N
8-Bit Microprocessor with OTP ROM
8 •
Product Specification (V1.2) 05.18.2007
(This specification is subject to change without further notice)
6.1.4 R3 (Status Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RST IOCS PS0 T P Z DC C
Bit 7 (RST): Bit of reset type
Set to “1” if wake-up from sleep on pin change, comparator status
change, or AD conversion completed. Set to “0” if wake-up from other
reset types
Bit 6 (IOCS): Select the Segment of IO control register
0 = Segment 0 (IOC50 ~ IOCF0) selected
1 = Segment 1 (IOC51 ~ IOCC1) selected
Bit 5 (PS0): Page select bits. PS0 is used to select a program memory page. When
executing a "JMP," "CALL," or other instructions which cause the
program counter to change (e.g., MOV R2, A), PS0 is loaded into the
11th bit of the program counter where it selects one of the available
program memory pages. Note that RET (RETL, RETI) instruction does
not change the PS0 bit. That is, the return address will always be back
to the page from where the subroutine was called, regardless of the
current PS0 bit setting.
PS0 Program Memory Page [Address]
0 Page 0 [000-3FF]
1 Page 1 [400-7FF]
Bit 4 (T): Time-out bit. Set to “1” by the "SLEP" and "WDTC" commands or during
power on; and reset to “0” by WDT time-out (see Section 6.5.2, The T
and P Status under STATUS Register for more details).
Bit 3 (P): Power-down bit. Set to “1” during power-on or by a "WDTC" command
and reset to “0” by a "SLEP" command (see Section 6.5.2, The T and P
Status under STATUS Register for more details).
Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is
zero.
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
6.1.5 R4 (RAM Select Register)
Bit 7: Set to “0” all the time
Bit 6: Used to select Bank 0 or Bank 1 of the register
Bits 5~0: Used to select a register (Address: 00~0F, 10~3F) in indirect addressing
mode
See the table under Section 6.1.3.1, Data Memory Configuration for data memory
configuration.