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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual 105
Host Software Interface
Example 2. Numerical Calculation
Assume the following incoming packet: SA DA Type F1 F5 54 79 E7 9E F5 CRC
S
0
= F5F1+7954 = 6F45, C
0
= 1
S
1
= 6F45 + 9EE7 + 1 = 0E2D, C
1
= 1
S
2
= 0E2C + 00F5 + 1 = 0F23, C
2
= 0
Check Sum = S
3
= 0F21+ 0 = 0F23
When all data bytes are written to the memory, the device writes the actual count. The device
writes the frame status to the RFD status word. The device asserts an interrupt to indicate the end of
receive processing. The driver can poll in memory for the frame status and mask the last interrupt.
6.5 Command Unit and Receive Unit Operation
6.5.1 Starting and Completing Control Commands
Software can issue control commands by writing to the RUC and CUC fields of the SCB command
word. The SCB CU and RU command fields are two fields in the lower byte of the SCB command
word, called the SCB command byte. Since the 8255x clears the SCB command byte when the
control command is accepted:
• Software must wait for this byte to be cleared before the next control command can be issued.
• CU and RU control commands must never be issued together in the same SCB write cycle.
The 8255x does not necessarily accept the control commands immediately after they are written to
the SCB since it may be engaged in higher priority tasks. For example, the device may be pre-
fetching new buffers, handling buffer switches, or finishing frame reception. When the device is
becomes available, it performs the start of control command sequence described below.
1. Reads the SCB command byte.
2. Reads the SCB general pointer.
3. The 8255x issues an internal request to the RU to perform an RU command acceptance
sequence if the RUC field is not zero.
4. The acceptance sequence for a CU command is performed immediately if the CUC field is not
zero.
After the CU and RU have completed the acceptance sequence, the 8255x updates the SCB status
according to the internal CU status, RU status, and interrupt requests.
6.5.2 Generating and Acknowledging Interrupts
When the CPU is interrupted by the 8255x, it should acknowledge the interrupt by setting the
corresponding acknowledge bits in the SCB interrupt acknowledge byte. When the CPU writes to
this byte, the corresponding interrupt bits are immediately cleared. If all interrupt bits are cleared,
the 8255x clears its INTA# line. If the interrupt service routine is likely to process all pending
interrupts, then all the bits can be acknowledged in one PCI write cycle.