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Video Capture Registers
3-79Video Capture PortSPRU629
3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM)
The transport stream interface system time clock compare MSB register
(TSISTCMPM) is used to generate an interrupt at some absolute time based
on the STC. TSISTCMPM holds the most-significant bit (MSB) of the absolute
time compare (ATC). Whenever the value in TSISTCMPM and TSISTCMPL
match the unmasked bits of the time kept by the STC hardware counter and
the STEN bit in TSICTL is set, the STC bit in VPIS is set. TSISTCMPM is shown
in Figure 3–45 and described in Table 3–30.
To prevent inaccurate comparisons caused by changing register bits, the
software should disable the system time clock interrupt (clear the STEN bit in
TSICTL) prior to writing to TSISTCMPM.
Figure 3–45. TSI System Time Clock Compare MSB Register (TSISTCMPM)
31 10
Reserved
ATC
R-0 R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Table 3–30. TSI System Time Clock Compare MSB Register (TSISTCMPM)
Field Descriptions
Description
Bit Field symval
†
Value
BT.656, Y/C Mode,
or Raw Data Mode
TSI Mode
31–1 Reserved – 0 Reserved. The reserved bit location is always read as 0. A
value written to this field has no effect.
0 ATC OF(value) 0–1 Not used. Contains the MSB of the absolute time
compare.
†
For CSL implementation, use the notation VP_TSISTCMPM_ATC_symval