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Index-1SPRU629
Index
A
ancillary data capture 3-31
ancillary data display 4-25
architecture 1-3
ATC bit
in TSISTCMPL 3-78
in TSISTCMPM 3-79
ATCM bit
in TSISTMSKL 3-80
in TSISTMSKM 3-81
B
BLKCAP bit
in VCACTL 3-53
in VCBCTL 3-68
BLKDIS bit 4-55
block diagrams
16/20-bit raw video capture FIFO
configuration 1-9
16/20-bit raw video display FIFO
configuration 1-11
8/10-bit locked raw video display FIFO
configuration 1-11
8/10-bit raw video capture FIFO
configuration 1-7
8/10-bit raw video display FIFO
configuration 1-10
BT.656 video capture FIFO configuration 1-6
BT.656 video display FIFO configuration 1-9
system time clock counter 3-39
TSI system 6-2
TSI video capture FIFO configuration 1-7
VIC port 6-2
video port 1-4
Y/C video capture FIFO configuration 1-8
Y/C video display FIFO configuration 1-12
boundary conditions
video capture 3-42
video display 4-33
BT.656 mode
blanking codes 4-12
BT.656 image display 4-12
capture channels 3-3
capture selection 3-18
capturing video 3-44
data sampling 3-8
display timing reference codes 4-9
displaying video 4-47
field and frame operation 3-17
FIFO overrun 3-45
FIFO packing 3-9
FIFO unpacking 4-13
image window and capture 3-6
timing reference codes 3-4
video capture 3-3
video display 4-9
C
CAPEVTCT1 bits 3-67
CAPEVTCT2 bits 3-67
capture channel reset 2-3
capture line boundary conditions 3-42
capture selection
BT.656 mode 3-18
raw data mode 3-33
TSI capture mode 3-40
Y/C mode 3-18
capturing data in TSI capture mode 3-47
capturing video
BT.656 mode 3-44
raw data mode 3-46
Y/C mode 3-44
Cb FIFO destination register (CBDST) 4-96
Cb FIFO source register (CBSRCx) 3-83