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Index-5SPRU629
registers (continued)
VIC port 6-5
VIC clock divider register (VICDIV) 6-9
VIC control register (VICCTL) 6-6
VIC input register (VICIN) 6-8
video capture 3-49
Cb FIFO source register (CBSRCx) 3-83
channel A control register (VCACTL) 3-53
channel A event count register
(VCAEVTCT) 3-67
channel A field 1 start register
(VCASTRT1) 3-58
channel A field 1 stop register
(VCASTOP1) 3-60
channel A field 2 start register
(VCASTRT2) 3-61
channel A field 2 stop register
(VCASTOP2) 3-62
channel A status register (VCASTAT) 3-50
channel A threshold register
(VCATHRLD) 3-65
channel A vertical interrupt register
(VCAVINT) 3-63
channel B control register (VCBCTL) 3-68
channel B event count register
(VCBEVTCT) 3-67
channel B field 1 start register
(VCBSTRT1) 3-58
channel B field 1 stop register
(VCBSTOP1) 3-60
channel B field 2 start register
(VCBSTRT2) 3-61
channel B field 2 stop register
(VCBSTOP2) 3-62
channel B status register (VCBSTAT) 3-50
channel B threshold register
(VCBTHRLD) 3-65
channel B vertical interrupt register
(VCBVINT) 3-63
Cr FIFO source register (CRSRCx) 3-83
FIFO 3-83
TSI clock initialization LSB register
(TSICLKINITL) 3-74
TSI clock initialization MSB register
(TSICLKINITM) 3-75
TSI control register (TSICTL) 3-72
TSI system time clock compare LSB register
(TSISTCMPL) 3-78
TSI system time clock compare mask LSB
register (TSISTMSKL) 3-80
TSI system time clock compare mask MSB
register (TSISTMSKM) 3-81
TSI system time clock compare MSB register
(TSISTCMPM) 3-79
TSI system time clock LSB register
(TSISTCLKL) 3-76
TSI system time clock MSB register
(TSISTCLKM) 3-77
TSI system time clock ticks interrupt register
(TSITICKS) 3-82
Y FIFO source register (YSRCx) 3-83
video display 4-52
Cb FIFO destination register (CBDST) 4-96
clipping register (VDCLIP) 4-85
control register (VDCTL) 4-55
counter reload register (VDRELOAD) 4-83
Cr FIFO destination register (CRDST) 4-96
default display value register
(VDDEFVAL) 4-86
display event register (VDDISPEVT) 4-84
field 1 image offset register
(VDIMGOFF1) 4-68
field 1 image size register (VDIMGSZ1) 4-70
field 1 timing register (VDFLDT1) 4-74
field 1 vertical blanking bit register
(VDVBIT1) 4-90
field 1 vertical blanking end register
(VDVBLKE1) 4-64
field 1 vertical blanking start register
(VDVBLKS1) 4-62
field 1 vertical synchronization end register
(VDVSYNE1) 4-80
field 1 vertical synchronization start register
(VDVSYNS1) 4-79
field 2 image offset register
(VDIMGOFF2) 4-71
field 2 image size register (VDIMGSZ2) 4-73
field 2 timing register (VDFLDT2) 4-75
field 2 vertical blanking bit register
(VDVBIT2) 4-92
field 2 vertical blanking end register
(VDVBLKE2) 4-67
field 2 vertical blanking start register
(VDVBLKS2) 4-65
field 2 vertical synchronization end register
(VDVSYNE2) 4-82
field 2 vertical synchronization start register
(VDVSYNS2) 4-81
field bit register (VDFBIT) 4-89
FIFO 4-96