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Video Port Control Registers
Video Port2-16 SPRU629
A DMA write throughput of at least 330 MBytes/s is required for the highest
display rate operation supported by 20-bit implementations of the video port.
C64x devices including the video port typically have more than enough DMA
bandwidth to support this throughput requirement. However when using multi-
ple high-bandwidth peripherals together, it is important to consider the total
DMA throughput required by the peripherals being used concurrently.
2.7 Video Port Control Registers
The video port control registers are listed in Table 2–4. See the device-specific
datasheet for the memory address of these registers.
After enabling the video port in the peripheral configuration register
(PERCFG), there should be a delay of 64 CPU cycles before accessing the
video port registers.
Table 2–4. Video Port Control Registers
Acronym Register Name Section
VPCTL Video Port Control Register 2.7.1
VPSTAT Video Port Status Register 2.7.2
VPIE Video Port Interrupt Enable Register 2.7.3
VPIS
Video Port Interrupt Status Register 2.7.4