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GPIO Registers
General Purpose I/O Operation5-22 SPRU629
Table 5–11. Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions
Bit field
†
symval
†
Value Description
31–23 Reserved – 0 Reserved. The reserved bit location is always read as 0.
A value written to this field has no effect.
22 PIPOL22 PIPOL22 bit determines the VCTL3 pin signal polarity
that generates an interrupt.
VCTL3ACTHI 0 Interrupt is caused by a low-to-high transition on the
VCTL3 pin.
VCTL3ACTLO 1
Interrupt is caused by a high-to-low transition on the
VCTL3 pin.
21
PIPOL21 PIPOL21 bit determines the VCTL2 pin signal polarity
that generates an interrupt.
VCTL2ACTHI 0 Interrupt is caused by a low-to-high transition on the
VCTL2 pin.
VCTL2ACTLO 1
Interrupt is caused by a high-to-low transition on the
VCTL2 pin.
20
PIPOL20 PIPOL20 bit determines the VCTL1 pin signal polarity
that generates an interrupt.
VCTL1ACTHI 0 Interrupt is caused by a low-to-high transition on the
VCTL1 pin.
VCTL1ACTLO 1
Interrupt is caused by a high-to-low transition on the
VCTL1 pin.
19–0
PIPOL[19–0] PIPOL[19–0] bit determines the corresponding VDATA[n]
pin signal polarity that generates an interrupt.
VDATAnACTHI 0 Interrupt is caused by a low-to-high transition on the
VDATA[n] pin.
VDATAnACTLO 1 Interrupt is caused by a high-to-low transition on the
VDATA[n] pin.
†
For CSL implementation, use the notation VP_PIPOL_PIPOLn_symval