Texas Instruments TMS320C64x DSP Network Card User Manual


 
Display Timing Examples
4-37Video Display PortSPRU629
The interlaced BT.656 vertical output timing is shown in Figure 434. The
BT.656 active field 1 is 244-lines high and active field 2 is 243-lines high. This
example shows the 480-line image window centered in the screen. This
results in an IMGVOFFn of 3 lines and also results in a nondata line at the end
of field 1 due to its extra active line.
The VBLNK and VSYNC signals are shown as they would be output for active-
low operation. Note that only one of the two signals is actually available exter-
nally. The VBLNK and VSYNC edges for field 1 occur at the end of an active
line so their XSTART/XSTOP values are set to 720 (start of blanking). For
field 2, VBLNK and VSYNC edges occur during the middle of the active
horizontal line so their XSTART/XSTOP values are set to 360. Note that, from
an analog standpoint, vertical blanking begins a half-line before digital blanking
so that VBLNKYSTART2 is set to 263 (with VBLNKXSTART2 set to 360) while
VBITSET2 is programmed to 264. For true BT.656 operation, neither VBLNK
nor VSYNC would be used.
The FLD output is setup to transition at the start of each analog field (start of
vertical blanking). Since EAV[F] transitions on lines 4 and 266, this requires
programming FBITCLR to 4, FBITSET to 266, FLD1YSTART to 1, and
FLD2YSTART to 263. Note that FLD2XSTRT is 360 so that the field indicator
output changes halfway through the line.
The ILCOUNT operation follows the description in section 4.1.2. ILCOUNT
resets to 1 at the first displayed line (FLCOUNT = VBLNKSTOPx + IMGVOFFx)
and stops counting at the last displayed pixel (IPCOUNT = IMGVSIZEx). The
operation during nondisplay time is not a requirement, it could continue count-
ing until the next FLCOUNT = VBLNKSTOPx + IMGVOFFx point or it could
reset immediately after IMGVSIZEx or when FLCOUNT is reset.
The active horizontal output column shows the output data during the active
portion of the horizontal line. It is assumed that the DVEN bit in VDCTL is set
to enable the default output.