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Video Port Control Registers
Video Port2-26 SPRU629
Table 2–9. Video Port Interrupt Status Register (VPIS) Field Descriptions (Continued)
Bit DescriptionValuesymvalfield
18 CCMPB Capture complete on channel B interrupt detected bit. (Data is not
in memory until the DMA transfer is complete.)
BT.656 or Y/C capture mode – CCMPB is set after capturing an
entire field or frame (when F1C, F2C, or FRMC in VCBSTAT are
set) depending on the CON, FRAME, CF1, and CF2 control bits in
VCBCTL.
Raw data mode – RDFE is not set, CCMPB is set when FRMC in
VCBSTAT is set (when the data counter = the combined
VCYSTOP/VCXSTOP value).
TSI capture mode – CCMPB is set when FRMC in VCBSTAT is set
(when the data counter = the combined VCYSTOP/VCXSTOP
value).
NONE 0 No interrupt is detected.
CLEAR 1 Interrupt is detected. Bit is cleared.
17
COVRB Capture overrun on channel B interrupt detected bit. COVRB is set
when data in the FIFO was overwritten before being read out (by
the DMA).
NONE 0 No interrupt is detected.
CLEAR 1 Interrupt is detected. Bit is cleared.
16
GPIO Video port general purpose I/O interrupt detected bit.
NONE 0 No interrupt is detected.
CLEAR 1 Interrupt is detected. Bit is cleared.
15
Reserved – 0 Reserved. The reserved bit location is always read as 0. A value
written to this field has no effect.
14 DCNA Display complete not acknowledged. Indicates that the F1D, F2D,
or FRMD bit that caused the display complete interrupt was not
cleared prior to the start of the next gating field or frame.
NONE 0 No interrupt is detected.
CLEAR 1 Interrupt is detected. Bit is cleared.
†
For CSL implementation, use the notation VP_VPIS_field_symval