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Video Port
Overview1-4 SPRU629
Figure 1–1. Video Port Block Diagram
Internal peripheral bus
Memory
mapped
registers
Raw video
display pipeline
Channel B
Channel A
Raw video
display pipeline
Y/C video
display pipeline
BT.656 display
pipeline
Y/C video
capture pipeline
Capture/display
buffer
(2560 bytes)
Raw video
capture pipeline
BT.656 capture
pipeline
TSI capture
pipeline
Raw video
capture pipeline
VDIN[19–10]
10
VDIN[19–0]
20
DMA interface
64
Capture/display
buffer
(2560 bytes)
10
10
8
20
20
10
20
20
Timing and
control logic
VCTL2
VCTL3
VCLK1
VCTL1
VCLK2
DMA interface
10 10
64
32
VDOUT[19–10]
10
VDOUT[19–0]
20
BT.656 capture
pipeline