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EMAC Port Registers
5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 49 and described
in Table 43.
Figure 49. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0
Reserved
PEND PEND PEND PEND PEND PEND PEND PEND
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 43. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 TX7PEND TX7PEND raw interrupt read (before mask)
6 TX6PEND TX6PEND raw interrupt read (before mask)
5 TX5PEND TX5PEND raw interrupt read (before mask)
4 TX4PEND TX4PEND raw interrupt read (before mask)
3 TX3PEND TX3PEND raw interrupt read (before mask)
2 TX2PEND TX2PEND raw interrupt read (before mask)
1 TX1PEND TX1PEND raw interrupt read (before mask)
0 TX0PEND TX0PEND raw interrupt read (before mask)
101
SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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