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EMAC Port Registers
5.5 Receive Control Register (RXCONTROL)
The receive control register (RXCONTROL) is shown in Figure 47 and described in Table 41.
Figure 47. Receive Control Register (RXCONTROL)
31 16
Reserved
R-0
15 1 0
Reserved RXEN
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 41. Receive Control Register (RXCONTROL) Field Descriptions
Bit Field Value Description
31-1 Reserved 0 Reserved
0 RXEN Receive DMA enable
0 Receive is disabled
1 Receive is enabled
99
SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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