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EMIC Module Registers
3.2.2 RPSTAT Registers
There are eight RPSTAT registers (RPSTAT0 thru RPSTAT7), one per receive event. This register
configuration is common to all C64x+ megamodules. The RPSTAT register details are shown in Figure 25
and described in Table 18.
Figure 25. RPSTAT Register
31 28 27 16
Reserved TIME
0000 R-0000 0000
15 8 7 4 3 2 1 0
CNT Reserved TIM_SM DIV_SM
R-0000 0000 0000 R-00 R-00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. RPSTAT Register Field Descriptions
Bit Field Value Description
31-28 Reserved Reserved
27-16 TIME Current time delay value
15-8 CNT Current divide by N value
7-4 Reserved Reserved
3-2 TIM_SM Time delay SM
00 Time delay SM in WAITING state
01 Time delay SM in DELAY state
10 Time delay SM in OUTPUT state
11 Reserved
1-0 DIV_SM Divide by N SM
00 Divide by N SM in WAITING state
01 Divide by N SM in DELAY state
10 Divide by N SM in OUTPUT state
11 Reserved
73
SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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