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EMAC Functional Architecture
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• Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames).
• The 32-bit frame-check sequence (CRC word).
All quantities are hexadecimal and are transmitted most-significant-byte first. The least-significant-bit
(LSB) is transferred first in each byte.
If the RXBUFFERFLOWEN bit in the MACCONTROL register is cleared while the pause time is nonzero,
then the pause time is cleared and a zero count pause frame is sent.
2.10.2 Data Transmission
The EMAC passes data to the PHY from the transmit FIFO (when enabled). Data is synchronized to the
transmit clock rate. Transmission begins when there are TXCELLTHRESH cells of 64 bytes each, or a
complete packet, in the FIFO.
2.10.2.1 Transmit Control
A jam sequence is output if a collision is detected on a transmit packet. If the collision was late (after the
first 64 bytes have been transmitted), the collision is ignored. If the collision is not late, the controller will
back off before retrying the frame transmission. When operating in full-duplex mode, the carrier sense
(MCRS) and collision-sensing (MCOL) modes are disabled.
2.10.2.2 CRC Insertion
If the SOP buffer descriptor PASSCRC flag is cleared, the EMAC generates and appends a 32-bit
Ethernet CRC onto the transmitted data. For the EMAC-generated CRC case, a CRC (or placeholder) at
the end of the data is allowed but not required. The buffer byte count value should not include the CRC
bytes, if they are present.
If the SOP buffer descriptor PASSCRC flag is set, then the last four bytes of the transmit data are
transmitted as the frame CRC. The four CRC data bytes should be the last four bytes of the frame and
should be included in the buffer byte count value. The MAC performs no error checking on the outgoing
CRC.
2.10.2.3 Adaptive Performance Optimization (APO)
The EMAC incorporates adaptive performance optimization (APO) logic that may be enabled by setting
the TXPACE bit in the MACCONTROL register. Transmission pacing to enhance performance is enabled
when the TXPACE bit is set. Adaptive performance pacing introduces delays into the normal transmission
of frames, delaying transmission attempts between stations, and reducing the probability of collisions
occurring during heavy traffic (as indicated by frame deferrals and collisions). These actions increase the
chance of a successful transmission.
When a frame is deferred, suffers a single collision, multiple collisions, or excessive collisions, the pacing
counter is loaded with an initial value of 31. When a frame is transmitted successfully (without
experiencing a deferral, single collision, multiple collision, or excessive collision), the pacing counter is
decremented by 1 down to 0.
If the pacing counter is zero, this allows a new frame to immediately attempt transmission (after one IPG).
If the pacing counter is nonzero, the frame is delayed by a pacing delay of approximately four inter-packet
gap delays. APO only affects the IPG preceding the first attempt at transmitting a frame; APO does not
affect the back-off algorithm for re-transmitted frames.
2.10.2.4 Interpacket-Gap (IPG) Enforcement
The measurement reference for the IPG of 96 bit times is changed depending on frame traffic conditions.
If a frame is successfully transmitted without collision and MCRS is de-asserted within approximately 48
bit times of MTXEN being de-asserted, then 96 bit times is measured from MTXEN. If the frame suffered a
collision or MCRS is not de-asserted until more than approximately 48 bit times after MTXEN is
de-asserted, then 96 bit times (approximately, but not less) is measured from MCRS.
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C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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