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4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ................. 86
4.12 MDIO User Access Register 0 (USERACCESS0) ................................................................ 87
4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) ............................................................ 88
4.14 MDIO User Access Register 1 (USERACCESS1) ................................................................ 89
4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) ............................................................ 90
5 EMAC Port Registers ......................................................................................................... 91
5.1 Transmit Identification and Version Register (TXIDVER) ........................................................ 95
5.2 Transmit Control Register (TXCONTROL) ......................................................................... 96
5.3 Transmit Teardown Register (TXTEARDOWN) ................................................................... 97
5.4 Receive Identification and Version Register (RXIDVER) ......................................................... 98
5.5 Receive Control Register (RXCONTROL) .......................................................................... 99
5.6 Receive Teardown Register (RXTEARDOWN) .................................................................. 100
5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .......................................... 101
5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ........................................ 102
5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ...................................................... 103
5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ................................................ 104
5.11 MAC Input Vector Register (MACINVECTOR) ................................................................... 105
5.12 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) .................................................... 106
5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ........................................... 107
5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ......................................... 108
5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ....................................................... 109
5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ................................................. 110
5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ............................................ 111
5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) .......................................... 112
5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ........................................................ 113
5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) .................................................. 114
5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .................. 115
5.22 Receive Unicast Enable Set Register (RXUNICASTSET) ...................................................... 118
5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) ......................................................... 119
5.24 Receive Maximum Length Register (RXMAXLEN) .............................................................. 120
5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) ......................................................... 121
5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) ......................... 122
5.27 Receive Channel 0-7 Flow Control Threshold Register (RXnFLOWTHRESH) .............................. 123
5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) ..................................... 124
5.29 MAC Control Register (MACCONTROL) .......................................................................... 125
5.30 MAC Status Register (MACSTATUS) ............................................................................. 127
5.31 Emulation Control Register (EMCONTROL) ...................................................................... 129
5.32 FIFO Control Register (FIFOCONTROL) ......................................................................... 130
5.33 MAC Configuration Register (MACCONFIG) ..................................................................... 131
5.34 Soft Reset Register (SOFTRESET) ................................................................................ 132
5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) .............................................. 133
5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) .............................................. 134
5.37 MAC Hash Address Register 1 (MACHASH1) ................................................................... 135
5.38 MAC Hash Address Register 2 (MACHASH2) ................................................................... 136
5.39 Back Off Test Register (BOFFTEST) .............................................................................. 137
5.40 Transmit Pacing Algorithm Test Register (TPACETEST) ....................................................... 138
5.41 Receive Pause Timer Register (RXPAUSE) ...................................................................... 139
5.42 Transmit Pause Timer Register (TXPAUSE) ..................................................................... 140
4
Contents SPRUEF8F–March 2006–Revised November 2010
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