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TXD
TX_SYNC
TX_CLK
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RX_SYNC
RX_CLK
MHZ_125_CLK
Device #1
TXD
TX_SYNC
TX_CLK
RXD
RX_SYNC
RX_CLK
MHZ_125_CLK
Device #2
TXD
TX_SYNC
TX_CLK
RXD
RX_SYNC
RX_CLK
MHZ_125_CLK
Device #n
125-MHz
zero-delay
clock buffer
125-MHz
XO
Low-skew
buffer
Zero-delay
clock buffer
External
logic
element
S3MII
switch
TX_CLK
TX_SYNC
P0_TXD
P0_RXD
P1_TXD
P1_RXD
Pn_TXD
Pn_RXD
RX_SYNC
RX_CLK
EMAC Functional Architecture
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In the case of the S3MII switch, where the switch has only one TX_SYNC for all ports, external logic is
needed to synchronize the TX_SYNC signals from multiple ports or TCI6486/C6472 devices. The TXD
signal from the multiple ports should also be synchronized using external logic since the clock-phase
relation of different TCI6486/C6472 devices can be different. Figure 8 demonstrates the example
mutli-PHY configuration for S3MII.
Figure 8. S3MII Switch Configuration
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C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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