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EMAC Functional Architecture
can be sent to only a single channel.
• The transmit path:
– Transmit DMA engine
The transmit DMA engine performs the data transfer between the device internal or external
memory and the transmit FIFO. It interfaces to the processor through the bus arbiter in the CPPI
buffer manager. This DMA engine is totally independent of the TCI6486/C6472 DSP EDMA.
– Transmit FIFO
The transmit FIFO consists of 24 cells of 64 bytes each and the associated control logic. This
enables a packet of 1518 bytes (standard Ethernet packet size) to be sent without the possibility of
under-run. The FIFO buffers data in preparation for transmission.
– MAC transmitter
The MAC transmitter formats frame data from the transmit FIFO and transmits the data using the
CSMA/CD access protocol. The frame CRC can be automatically appended, if required. The MAC
transmitter also detects transmission errors and passes statistics to the statistics registers.
• Statistics logic
The statistics logic RAM counts and stores the Ethernet statistics, keeping track of 36 different
Ethernet packet statistics.
• State RAM
The state RAM contains the head descriptor pointers and completion pointers registers for both
transmit and receive channels.
• Interrupt controller
The interrupt controller contains the interrupt-related registers and logic. The 18 raw EMAC interrupts
are input to this sub-module and masked module interrupts are output.
• Control registers and logic
The EMAC is controlled by a set of memory-mapped registers. The control logic also signals transmit,
receive, and status related interrupts to the CPU through the EMIC module.
• Clock and reset logic
The clock and reset sub-module generates all the clocks and resets for the EMAC peripheral.
2.9.2 EMAC Module Operational Overview
After reset, initialization, and configuration of the EMAC, the application software running on the host may
initiate transmit operations. Transmit operations are initiated by host writes to the appropriate transmit
channel head descriptor pointer contained in the state RAM block. The transmit DMA controller then
fetches the first packet in the packet chain from memory. The DMA controller writes the packet into the
transmit FIFO in bursts of 64-byte cells. The MAC transmitter initiates the packet transmission when either
the threshold number of cells (configurable via TXCELLTHRESH in the FIFOCONTROL register) have
been written to the transmit FIFO, or a complete packet has been written, whichever is smaller. The SYNC
block transmits the packet over one of the MII interfaces in accordance with the 802.3 protocol. The
statistics block counts transmit statistics.
Receive operations are initiated by host writes to the appropriate receive channel head descriptor pointer
after host initialization and configuration. The SYNC sub-module receives packets and strips off the
Ethernet related protocol. The packet data is input to the MAC receiver, which checks for address match
(in conjunction with the receive address block) and processes errors. Accepted packets are written to the
receive FIFO in bursts of 64-byte cells. The receive DMA controller then writes the packet data to memory.
The statistics block counts receive statistics.
The EMAC module operates independently of the CPU. It is configured and controlled by its register set
mapped into device memory. Information about data packets is communicated using 16-byte descriptors.
For transmit operations, each 16-byte descriptor describes a packet or packet fragment in the system's
internal or external memory. For receive operations, each 16-byte descriptor represents a free packet
buffer or buffer fragment. On both transmit and receive, an Ethernet packet is allowed to span one or
more memory fragments, represented by one 16-byte descriptor per fragment. In typical operation, there is
only one descriptor per receive buffer, but transmit packets may be fragmented, depending on the
software architecture.
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SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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