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Table 36. Ethernet Media Access Controller (EMAC) Registers (continued)
Offset Acronym Register Description See
15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 5.28
160h MACCONTROL MAC Control Register Section 5.29
164h MACSTATUS MAC Status Register Section 5.30
168h EMCONTROL Emulation Control Register Section 5.31
16Ch FIFOCONTROL FIFO Control Register Section 5.32
170h MACCONFIG MAC Configuration Register Section 5.33
174h SOFTRESET Soft Reset Register Section 5.34
1D0h MACSRCADDRLO MAC Source Address Low Bytes Register Section 5.35
1D4h MACSRCADDRHI MAC Source Address High Bytes Register Section 5.36
1D8h MACHASH1 MAC Hash Address Register 1 Section 5.37
1DCh MACHASH2 MAC Hash Address Register 2 Section 5.38
1E0h BOFFTEST Back Off Test Register Section 5.39
1E4h TPACETEST Transmit Pacing Algorithm Test Register Section 5.40
1E8h RXPAUSE Receive Pause Timer Register Section 5.41
1ECh TXPAUSE Transmit Pause Timer Register Section 5.42
500h MACADDRLO MAC Address Low Bytes Register, Used in Receive Address Section 5.43
Matching
504h MACADDRHI MAC Address High Bytes Register, Used in Receive Address Section 5.44
Matching
508h MACINDEX MAC Index Register Section 5.45
600h TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register Section 5.46
604h TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register Section 5.46
608h TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register Section 5.46
60Ch TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register Section 5.46
610h TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register Section 5.46
614h TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register Section 5.46
618h TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register Section 5.46
61Ch TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register Section 5.46
620h RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register Section 5.47
624h RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register Section 5.47
628h RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register Section 5.47
62Ch RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register Section 5.47
630h RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register Section 5.47
634h RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register Section 5.47
638h RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register Section 5.47
63Ch RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register Section 5.47
640h TX0CP Transmit Channel 0 Completion Pointer (Interrupt Section 5.48
Acknowledge) Register
644h TX1CP Transmit Channel 1 Completion Pointer (Interrupt Section 5.48
Acknowledge) Register
648h TX2CP Transmit Channel 2 Completion Pointer (Interrupt Section 5.48
Acknowledge) Register
64Ch TX3CP Transmit Channel 3 Completion Pointer (Interrupt Section 5.48
Acknowledge) Register
650h TX4CP Transmit Channel 4 Completion Pointer (Interrupt Section 5.48
Acknowledge) Register
654h TX5CP Transmit Channel 5 Completion Pointer (Interrupt Section 5.48
Acknowledge) Register
658h TX6CP Transmit Channel 6 Completion Pointer (Interrupt Section 5.48
Acknowledge) Register
92
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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