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EMAC Port Registers
5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)
The receive channel 0-7 completion pointer register (RXnCP) is shown in Figure 91 and described in
Table 85.
Figure 91. Receive Channel n Completion Pointer Register (RXnCP)
31 16
RXnCP
R/W-x
15 0
RXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset
Table 85. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
Bit Field Value Description
31-0 RXnCP Receive channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be de-asserted.
147
SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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