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4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 34 and
described in Table 27.
Figure 34. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
31 16
Reserved
R-0
15 2 1 0
LINKINT
Reserved
MASKED
R-0 R/WC-0
LEGEND: R = Read only; R/WC = Read/Write 1 to clear; -n = value after reset
Table 27. MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field
Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1-0 LINKINTMASKED MDIO Link change interrupt, masked value. hen asserted, a bit indicates that there was an MDIO
link change event (a change in the LINK register) corresponding to the PHY address in the
USERPHYSEL register and the corresponding LINKINTENB bit was set. LINKINTRAW[0] and
LINKINTRAW[1] correspond to USERPHYSEL0 and USERPHYSEL1, respectively. Writing a 1 will
clear the event and writing 0 has no effect.
82
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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