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EMAC Functional Architecture
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Table 11 summarizes the individual EMAC and MDIO signals for the S3MII interface.
Table 11. EMAC and MDIO Signals for S3MII Interface
Signal Name I/O Description
TX_CLK O Transmit clock. The transmit clock is a continuous clock that provides the timing reference for
transmit operations. The TXD and TX_SYNC signals are tied to this clock. This clock is 125 MHz at
10- and 100-Mbps operations.
TX_SYNC O Transmit Synchronization. The TX_SYNC signal is used to synchronize the TXD data signal. This
signal is synchronized with a 125-MHz clock.
TXD O Transmit Data. The transmit data is synchronized with a transmit clock and a transmit
synchronization signal.
RX_CLK I Transmit clock. The transmit clock is a continuous clock that provides the timing reference for
transmit operations. The RXD and RX_SYNC signals are tied to this clock. This clock is 125 MHz at
10- and 100-Mbps operations.
RX_SYNC I Receive Synchronization. The RX_SYNC signal is used to synchronize the RXD data signal. This
signal is synchronized with a 125-MHz clock.
RXD I Receive Data. The receive data is synchronized with a receive clock and a receive synchronization
signal.
MDCLK O Management data clock (MDCLK). The MDIO data clock is sourced by the MDIO module. It
synchronizes MDIO data access operations done on the MDIO pin. The frequency of this clock is
controlled by the CLKDIV bits in the MDIO control register (CONTROL).
MDIO I/O Management data input output (MDIO). The MDIO pin drives PHY management data into and out of
the PHY via an access frame consisting of start-of-frame, read/write indication, PHY address,
register address, and data-bit cycles. The MDIO pin acts as an output for everything except the
data-bit cycles, when the pin acts as an input for read operations.
The TCI6486/C6472 device S3MII pins are multiplexed with other non-RGMII pins. When using the
S3MII0 port on EMAC0, there are no restrictions on the available EMAC1 Ethernet interfaces (RMII1,
S3MII1, and RGMII1 are useable). When using the S3MII1 port on EMAC1, the EMAC0 Ethernet
interfaces not available due to pin multiplexing are GMII0/MII0. The RMII0, S3MII0, and RGMII0 ports are
available on EMAC0 Ethernet interfaces.
In a multi-PHY situation, where PHY has only one TX_SYNC for all ports, external logic is needed to
synchronize the TX_SYNC signals from multiple ports or TCI6486/C6472 devices. The TXD signal from
the multiple ports should also be synchronized using external logic since the clock-phase relation of
different TCI6486/C6472 devices can be different. Figure 7 demonstrates the example mutli-PHY
configuration for S3MII.
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C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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