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5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 60 and described
in Table 54.
Figure 60. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
31 16
Reserved
R-0
15 2 1 0
HOST STAT
Reserved
PEND PEND
R-0 R-0 R-0
LEGEND: R/W = R = Read only; -n = value after reset
Table 54. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
Bit Field Value Description
31-2 Reserved 0 Reserved
1 HOSTPEND Host pending interrupt (HOSTPEND); masked interrupt read
0 STATPEND Statistics pending interrupt (STATPEND); masked interrupt read
112
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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