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5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER)
The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 70 and
described in Table 64.
Figure 70. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
31 16
Reserved
R-0
15 0
RXnFREEBUF
WI-0
tLEGEND: R = Read only; R/W = Read/Write; WI = Write to increment; -n = value after reset
Table 64. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15-0 RXnFREEBUF Receive free buffer count. These bits contain the count of free buffers available. The
RXFILTERTHRESH value is compared with this field to determine if low priority frames should be
filtered. The RXnFLOWTHRESH value is compared with this field to determine if receive flow
control should be issued against incoming packets (if enabled). This is a write-to-increment field.
This field rolls over to zero on overflow. If hardware flow control or QOS is used, the host must
initialize this field to the number of available buffers (one register per channel). The EMAC
decrements (by the number of buffers in the received frame) the associated channel register for
each received frame. The host must write this field with the number of buffers that have been freed
due to host processing.
124
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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