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47 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................ 105
48 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) Field Descriptions.................................. 106
49 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions........................ 107
50 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions ...................... 108
51 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions .................................... 109
52 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions.............................. 110
53 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions ......................... 111
54 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions........................ 112
55 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ..................................... 113
56 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ............................... 114
57 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field
Descriptions............................................................................................................... 115
58 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions ................................... 118
59 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ...................................... 119
60 Receive Maximum Length Register (RXMAXLEN) Field Descriptions............................................ 120
61 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions....................................... 121
62 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ...... 122
63 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions.............. 123
64 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions ..................... 124
65 MAC Control Register (MACCONTROL) Field Descriptions ....................................................... 125
66 MAC Status Register (MACSTATUS) Field Descriptions........................................................... 127
67 Emulation Control Register (EMCONTROL) Field Descriptions ................................................... 129
68 FIFO Control Register (FIFOCONTROL) Field Descriptions....................................................... 130
69 MAC Configuration Register (MACCONFIG) Field Descriptions .................................................. 131
70 Soft Reset Register (SOFTRESET) Field Descriptions............................................................. 132
71 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ........................... 133
72 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................ 134
73 MAC Hash Address Register 1 (MACHASH1) Field Descriptions................................................. 135
74 MAC Hash Address Register 2 (MACHASH2) Field Descriptions................................................. 136
75 Back Off Test Register (BOFFTEST) Field Descriptions ........................................................... 137
76 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions .................................... 138
77 Receive Pause Timer Register (RXPAUSE) Field Descriptions................................................... 139
78 Transmit Pause Timer Register (TXPAUSE) Field Descriptions .................................................. 140
79 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions .......................................... 141
80 MAC Address High Bytes Register (MACADDRHI) Field Descriptions........................................... 142
81 MAC Index Register (MACINDEX) Field Descriptions .............................................................. 143
82 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions................... 144
83 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions ................... 145
84 Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions.................................. 146
85 Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions .................................. 147
86 Statistics Register Field Descriptions.................................................................................. 148
87 EMAC/MDIO Revision History.......................................................................................... 159
9
SPRUEF8F–March 2006–Revised November 2010 List of Tables
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