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EMAC Functional Architecture
To add a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time, the
software application writes the pointer to the descriptor or first descriptor of a list to the corresponding
HDP register. Note that the last descriptor in the list must have its next pointer cleared so that the EMAC
can detect the end of the list. If only a single descriptor is added, its next descriptor pointer must be
initialized to zero.
The HDP register must never be written to a second time while a previous list is active. To add additional
descriptors to a descriptor list already owned by the EMAC, the NULL next pointer of the last descriptor of
the previous list is patched with a pointer to the first descriptor in the new list. The list of new descriptors
to be appended to the existing list must itself be NULL terminated before the pointer patch is performed.
If the EMAC reads the next pointer of a descriptor as NULL in the instant before an application appends
additional descriptors to the list by patching the pointer, this may result in a race condition. Thus, the
software application must always examine the Flags field of all EOP packets, looking for a special flag
called end-of-queue (EOQ). The EOQ flag is set by the EMAC on the last descriptor of a packet when the
descriptor's next pointer is NULL, allowing the EMAC to indicate to the software application that it has
reached the end of the list. When the software application sees the EOQ flag set, and there are more
descriptors to process, the application may then submit the new list or missed list portion by writing the
new list pointer to the same HDP register that started the process.
This process applies when adding packets to a transmit list, and empty buffers to a receive list.
2.5.3 Transmit and Receive EMAC Interrupts
The EMAC processes descriptors in linked list chains (Section 2.5.1), using the linked list queue
mechanism (Section 2.5.2).
The EMAC synchronizes the descriptor list processing by using interrupts to the software application. The
interrupts are controlled by the application by using the interrupt masks, global interrupt enable, and the
completion pointer register (CP). This register is also called interrupt acknowledge register.
As the EMAC supports eight channels for both transmit and receive, there are eight CP registers for both.
They are designated as:
• TXnCP: Transmit Channel n Completion Pointer (Interrupt Acknowledge) Register
• RXnCP: Receive Channel n Completion Pointer (Interrupt Acknowledge) Register
These registers serve two purposes. When read, they return the pointer to the last descriptor that the
EMAC has processed. When written by the software application, the value represents the last descriptor
processed by the software application. If these two values do not match, the interrupt is active.
The system configuration determines whether an active interrupt can interrupt the CPU. In general, the
global interrupt for EMAC and MDIO must be enabled in the EMIC module, and it also must be mapped in
the DSP interrupt controller and enabled as a CPU interrupt. If the system is configured properly, the
interrupt for a specific receive or transmit channel executes under these conditions when the
corresponding interrupt is enabled in the EMAC using the RXINTMASKSET or TXINTMASKSET registers.
The current state of the receive or transmit channel interrupt can be examined directly by the software
application by reading the RXINTSTATRAW and TXINTSTATRAW registers, whether or not the interrupt
is enabled.
Interrupts are acknowledged when the application software updates the value of TXnCP or RXnCP with a
value that matches the internal value kept by the EMAC.
This mechanism ensures that the application software never misses an EMAC interrupt, as the interrupt
and its acknowledgment are tied directly to the actual buffer descriptors processing.
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SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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