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EMAC Functional Architecture
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Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then
acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the
queue's associated RX completion pointer in the receive DMA state RAM.
The data written by the host (buffer descriptor address of the last processed buffer) is compared to the
data in the register written by the EMAC (address of last buffer descriptor used by the EMAC). If the two
values are not equal, indicating that the EMAC has received more packets than the CPU has processed
interrupts for, the receive packet completion interrupt signal remains asserted. If the two values are equal,
indicating that the host has processed all packets that the EMAC has received, the pending interrupt is
de-asserted. Reading the RXnCP register displays the value that the EMAC is expecting.
The EMAC write to the completion pointer stores the value in the state RAM. The CPU written value does
not change the register value. The host-written value is compared to the register content, which was
written by the EMAC. If the two values are equal, then the interrupt is removed; otherwise the interrupt
remains asserted. The host may process multiple packets prior to acknowledging an interrupt, or the host
may acknowledge interrupts for every packet.
2.17.1.3 Statistics Interrupt
The statistics level interrupt (STATPEND) is issued when any statistics value is greater than or equal to
8000 0000h, if it has been enabled by the STATMASK bit in the MACINTMASKSET register. The statistics
interrupt is removed by writing to decrement any statistics value greater than 8000 0000h. The interrupt
remains asserted as long as the most-significant-bit of any statistics value is set.
2.17.1.4 Host Error Interrupt
The host error interrupt (HOSTPEND) is issued, if enabled, under error conditions due to the handling of
buffer descriptors detected during transmit or receive DMA transactions. The failure of the software
application to supply properly formatted buffer descriptors results in this error. The error bit can only be
cleared by resetting the EMAC module in hardware.
The host error interrupt is enabled by setting the HOSTMASK bit in the MACINTMASKSET register. The
host error interrupt is disabled by clearing the appropriate bit in the MACINTMASKCLEAR register. The
raw and masked host error interrupt status may be read by reading the MACINTSTATRAW and
MACINTSTATMASKED registers, respectively.
Transmit host error conditions include:
• SOP error
• Ownership bit not set in SOP buffer
• Zero next buffer descriptor pointer without EOP
• Zero buffer pointer
• Zero buffer length
• Packet length error
Receive host error conditions include:
• Ownership bit not set in input buffer
• Zero buffer pointer
2.17.2 MDIO Module Interrupt Events and Requests
The MDIO module generates two interrupt events, as follows:
• LINKINT: Serial interface link change interrupt. Indicates a change in the state of the PHY link.
• USERINT: Serial interface user command event complete interrupt.
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C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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