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2.10.2.7 Speed, Duplex, and Pause Frame Support
The MAC can operate in half-duplex or full-duplex mode at 10 Mbps or 100 Mbps, and can operate in full
duplex only in 1000 Mbps. Pause frame support is included in 10/100/1000 Mbps modes as configured by
the host.
2.11 Packet Receive Operation
2.11.1 Receive DMA Host Configuration
To configure the receive DMA for operation, the host must perform the following actions:
• Initialize the receive addresses
• Initialize the RXnHDP registers to zero
• Write the MACHASH1 and MACHASH2 registers, if hash matching multicast addressing is desired
• Initialize the RXnFREEBUFFER, RXnFLOWTHRESH, and RXFILTERLOWTHRESH registers, if flow
control is to be enabled
• Enable the desired receive interrupts using the RXINTMASKSET and RXINTMASKCLEAR registers
• Set the appropriate configuration bits in the MACCONTROL register
• Write the RXBUFFEROFFSET register value (typically zero)
• Set up the receive channel(s) buffer descriptors and initialize the RXnHDP registers
• Enable the receive DMA controller by setting the RXEN bit in the RXCONTROL register
• Configure and enable the receive operation, as desired, in the RXMBPENABLE register and by using
the RXUNICASTSET and RXUNICASTCLEAR registers
2.11.2 Receive Channel Enabling
Each of the eight receive channels has an enable bit (RXCHnEN) in the RXUNICASTSET register that is
controlled using the RXUNICASTSET and RXUNICASTCLEAR registers. The RXCHnEN bits determine
whether the given channel is enabled (when set to 1) to receive frames with a matching unicast or
multicast destination address.
The RXBROADEN bit in the RXMBPENABLE register determines if broadcast frames are enabled or
filtered. If broadcast frames are enabled, then they are copied to only a single channel selected by the
RXBROADCH field of RXMBPENABLE register.
The RXMULTEN bit in the RXMBPENABLE register determines if hash matching multicast frames are
enabled or filtered. Incoming multicast addresses (group addresses) are hashed into an index in the hash
table. If the indexed bit is set, the frame hash will match and it will be transferred to the channel selected
by the RXMULTCH field when multicast frames are enabled. The multicast hash bits are set in the
MACHASH1 and MACHASH2 registers.
The RXPROMCH bits in the RXMBPENABLE register select the promiscuous channel to receive frames
selected by the RXCMFEN, RXCSFEN, RXCEFEN, and RXCAFEN bits. These four bits allow reception of
MAC control frames, short frames, error frames, and all frames (promiscuous), respectively.
The address RAM can be configured to set multiple unicast and/or multicast addresses to a given channel
(if the match bit is set in the RAM). Multicast addresses in the RAM are enabled by the RXUNICASTSET
register and not by the RXMULTEN bit in the RXMBPENABLE register. The RXMULTEN bit enables the
hash multicast match only. The address RAM takes precedence over the hash match.
If a multicast packet is received that hash matches (multicast packets enabled), but is filtered in the RAM,
then the packet is filtered. If a multicast packet does not hash match, regardless of whether or not hash
matching is enabled, but matches an enabled multicast address in the RAM, then the packet will be
transferred to the associated channel.
2.11.3 Receive Channel Addressing
The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet
reception, all the address RAM locations should be initialized, including locations to be unused. The
system software is responsible for adding and removing addresses from the RAM.
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C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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