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EMAC Port Registers
5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP)
The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in Figure 89 and
described in Table 83.
Figure 89. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP)
31 16
RXnHDP
R/W-x
15 0
RXnHDP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset
Table 83. Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions
Bit Field Value Description
31-0 RXnHDP Receive channel n DMA Head Descriptor pointer. Writing a receive DMA buffer descriptor address
to this location allows receive DMA operations in the selected channel when a channel frame is
received. Writing to these locations when they are nonzero is an error (except at reset). Host
software must initialize these locations to zero on reset.
145
SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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