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2.5.5.16 Control Flag
The EMAC sets this flag in the SOP buffer descriptor if the received packet is an EMAC control frame and
was not discarded because the RXCMFEN bit was set in the RXMBPENABLE register.
2.5.5.17 Overrun Flag
The EMAC sets this flag in the SOP buffer descriptor if the received packet was aborted due to a receive
overrun.
2.5.5.18 Code Error (CODEERROR) Flag
The EMAC sets this flag in the SOP buffer descriptor if the received packet contained a code error and
was not discarded because the RXCEFEN bit was set in the RXMBPENABLE register.
2.5.5.19 Alignment Error (ALIGNERROR) Flag
The EMAC sets this flag in the SOP buffer descriptor if the received packet contained an alignment error
and was not discarded because the RXCEFEN bit was set in the RXMBPENABLE register.
2.5.5.20 CRC Error (CRCERROR) Flag
The EMAC sets this flag in the SOP buffer descriptor if the received packet contained a CRC error and
was not discarded because the RXCEFEN bit was set in the RXMBPENABLE register.
2.5.5.21 No-Match (NOMATCH) Flag
The EMAC sets this flag in the SOP buffer descriptor if the received packet did not pass any of the
EMAC's address match criteria and was not discarded because the RXCAFEN bit was set in the
RXMBPENABLE register. Although the packet is a valid Ethernet data packet, it is only received because
the EMAC is in promiscuous mode.
2.6 Communications Port Programming Interface (CPPI)
The CPPI refers to the data structures used by the EMAC to describe transmit and receive packets and
the application programming interface to manipulate the data structures. The CPPI maximizes the
efficiency of communication between host processor and EMAC. It minimizes the host interaction,
maximizes the memory use efficiency, and maximizes the symmetry between transmit and receive
operations. Some of the important features of the CPPI include distributed buffer management, protocol
independent packet level interface, support for multichannel/multi-priority queuing, and support for multiple
buffer queues. The details of transmit and receive operations and buffer descriptors are covered in
Section 2.5.
2.7 Ethernet Multicore Interrupt Combiner (EMIC) Module
The ethernet multicore interrupt combiner (EMIC) module is designed to efficiently route a single set of
interrupts from EMAC and MDIO to multiple cores on a multicore device. It also incorporates interrupt
pacing functionality for the Ethernet TX and RX pulse interrupts. The EMIC module uses the pulse
interrupts to incorporate some of its pacing functionality.
A high-level block diagram of the EMIC is shown in Figure 14. The following components, as shown in
Figure 14, make up the EMIC:
• Pacer Block which consists of:
– Timed-Delay state machine (TSM)
– Divide State Machine (DSM)
• Transmit Pacer and Interrupt Combiner (TPIC) which consists of:
– Pacer block per TX event
– Interrupt combiner
• Receive Pacer and Interrupt Combiner (RPIC) which consists of:
– Pacer block per TX event
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C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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