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5.50 Network Statistics Registers
The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are
cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL
register is set, all statistics registers are write-to-decrement. The value written is subtracted from the
register value with the result stored in the register. If a value greater than the statistics value is written,
then zero is written to the register (writing FFFF FFFFh clears a statistics location). When the GMIIEN bit
is cleared, all statistics registers are read/write (normal write direct, so writing 0000 0000h clears a
statistics location). All write accesses must be 32-bit accesses.
The statistics interrupt (STATPEND) is issued, if enabled, when any statistics value is greater than or
equal to 8000 0000h. The statistics interrupt is removed by writing to decrement any statistics value
greater than 8000 0000h. The statistics are mapped into internal memory space and are 32-bits wide. All
statistics roll over from FFFF FFFFh to 0000 0000h.
The network statistics register is shown in Figure 92 and described in Table 86.
Figure 92. Statistics Register
31 16
COUNT
R/W-0
15 0
COUNT
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 86. Statistics Register Field Descriptions
Bit Field Value Description
31-0 COUNT Count
5.50.1 Good Receive Frames Register (RXGOODFRAMES)
The total number of good frames received on the EMAC. A good frame is defined as having all of the
following:
• Any data or MAC control frame that matched a unicast, broadcast, or multicast address, or matched
due to promiscuous mode
• Was of length 64 to RXMAXLEN bytes inclusive
• Had no CRC error, alignment error, or code error
See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this
statistic.
5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES)
The total number of good broadcast frames received on the EMAC. A good broadcast frame is defined as
having all of the following:
• Any data or MAC control frame that was destined for address FF-FF-FF-FF-FF-FFh only
• Was of length 64 to RXMAXLEN bytes inclusive
• Had no CRC error, alignment error, or code error
See Section 2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this
statistic.
148
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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