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Figure 24. RPCFG Register
31 28 27 16
Reserved TIME_CFG
0000 R/W-0000 0000
15 8 7 4 3 2 1 0
CNT_CFG Reserved TU CU TR CR
R/W-0000 0000 0000 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. RPCFG Register Field Descriptions
Bit Field Value Description
31-28 Reserved Reserved
27-16 TIME_CFG Time delay configuration value
15-8 CNT_CFG Divide by N configuration value
7-4 Reserved Reserved
3 TU Write-only bit; reads return 0
0 N/A
1 Enables writes to TIME_CFG
2 CU Write-only bit; reads return 0
0 N/A
1 Enables writes to CNT_CFG
1 TR Write-only bit; reads return 0
0 N/A
1 Resets the timer counter
0 CR Write-only bit; reads return 0
0 N/A
1 Resets the divide by N count
72
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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