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EMAC Functional Architecture
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2.1.3 GMII Clocking
The GMII interface is available only on EMAC0 and requires two clock sources generated internally, the
peripheral bus clock and the RFTCLK inputs to the EMAC module. SYSCLK14 is programmed to /4 for
this interface to provide a 125-MHz clock to the RFTCLK input of EMAC. The GMII interface is selected by
programming MACSEL0 to 2 (010b). Transmit and receive clock sources for 10/100-Mbps modes are
provided from an external PHY via the MTCLK and MRCLK pins. For 1000-Mbps mode, the receive clock
is provided by an external PHY via the MRCLK pin. For transmit in 1000-Mbps mode, the clock is sourced
synchronous with the data, and is provided by the EMAC to be output on the GMTCLK pin.
For timing purposes, data in 10/100-Mbps mode is transmitted and received with reference to MTCLK and
MRCLK, respectively. For 1000-Mbps mode, receive timing is the same, but transmit is relative to
GMTCLK.
2.1.4 RGMII Clocking
The RGMII interface is selected by programming MACSEL0 to 3 (011b) and MACSEL1 to 2 (10b). RGMII
requires 4 internally generated clocks; peripheral bus clock and three reference clocks. The EMAC drives
the transmit clock, while an external PHY generates the receive clock. The reference clock drives the
device pin that gives the 125-MHz clock to the PHY; this enables the PHY to generate the receive clock
that is sent to EMAC.
The RGMII protocol takes a GMII data stream and turns it into an interface with half of the data bus width
and sends the same amount of data with a reduced pinout. The RGMII protocol also allows for dynamic
switching of the mode between 10/100/1000-Mbps modes. This negotiation data is embedded in the
incoming data stream from the external PHY. For timing purposes, data is transmitted and received with
respect to MTCLK and MRCLK, respectively.
The RGMII interface has separate I/O pins from the other EMAC pins because the interface voltage is
different from the other interfaces.
2.1.5 S3MII Clocking
S3MII mode is selected by programming MACSEL0 to 5 (101b) and MACSEL1 to 1 (01b). The S3MII
gasket needs a 125-MHz continuous clock (125_CLK) supplied by an external source. It also needs a
peripheral bus clock as input. MTCLK and MRCLK are fixed at 125 MHz.
2.2 Memory Map
The EMAC includes an internal memory that holds information about the Ethernet packets that are
received or transmitted. This internal RAM is 2K x 32 bits in size. The data can be written to and read from
the EMAC internal memory via either the EMAC or the CPU. It stores buffer descriptors that are 4 words
(16 bytes) deep. This 8K local memory holds enough information to transfer up to 512 Ethernet packets
without CPU intervention.
The packet buffer descriptors can be put in internal processor memory (L2) on the TCI6486/C6472 device.
There are some trade-offs in terms of cache performance and throughput when the descriptors are put in
L2 versus when they are put in EMAC internal memory. The cache performance improves when the buffer
descriptors are put in the internal memory. However, the EMAC throughput is better when the descriptors
are put in the local EMAC RAM.
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C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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