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EMAC Port Registers
5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 55 and described
in Table 49.
Figure 55. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
31 16
Reserved
R-0
15 8 7 6 5 4 3 2 1 0
RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
Reserved
PEND PEND PEND PEND PEND PEND PEND PEND
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 49. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
Bit Field Value Description
31-8 Reserved 0 Reserved
7 RX7PEND RX7PEND raw interrupt read (before mask)
6 RX6PEND RX6PEND raw interrupt read (before mask)
5 RX5PEND RX5PEND raw interrupt read (before mask)
4 RX4PEND RX4PEND raw interrupt read (before mask)
3 RX3PEND RX3PEND raw interrupt read (before mask)
2 RX2PEND RX2PEND raw interrupt read (before mask)
1 RX1PEND RX1PEND raw interrupt read (before mask)
0 RX0PEND RX0PEND raw interrupt read (before mask)
107
SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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