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5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)
The transmit channel 0-7 completion pointer register (TXnCP) is shown in Figure 90 and described in
Table 84.
Figure 90. Transmit Channel n Completion Pointer Register (TXnCP)
31 16
TXnCP
R/W-x
15 0
TXnCP
R/W-x
LEGEND: R/W = Read/Write; -n = value after reset
Table 84. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
Bit Field Value Description
31-0 TXnCP Transmit channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be de-asserted.
146
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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