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EMAC Port Registers
5.41 Receive Pause Timer Register (RXPAUSE)
The receive pause timer register (RXPAUSE) is shown in Figure 83 and described in Table 77.
Figure 83. Receive Pause Timer Register (RXPAUSE)
31 16
Reserved
R-0
15 0
PAUSETIMER
R-0
LEGEND: R = Read only; -n = value after reset
Table 77. Receive Pause Timer Register (RXPAUSE) Field Descriptions
Bit Field Value Description
31-16 Reserved 0 Reserved
15-0 PAUSETIMER Receive pause timer value. These bits allow the contents of the receive pause timer to be
observed. The receive pause timer is loaded with FF00h when the EMAC sends an outgoing pause
frame (with pause time of FFFFh). The receive pause timer is decremented at slot time intervals. If
the receive pause timer decrements to 0, then another outgoing pause frame is sent and the
load/decrement process is repeated.
139
SPRUEF8F–March 2006–Revised November 2010 C6472/TCI6486 EMAC/MDIO
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