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Table 36. Ethernet Media Access Controller (EMAC) Registers (continued)
Offset Acronym Register Description See
27Ch FRAME1024TUP Transmit and Receive 1024 to RXMAXLEN Octet Frames Section 5.50.32
Register
280h NETOCTETS Network Octet Frames Register Section 5.50.33
284h RXSOFOVERRUNS Receive FIFO or DMA Start-of-Frame Overruns Register Section 5.50.34
288h RXMOFOVERRUNS Receive FIFO or DMA Middle-of-Frame Overruns Register Section 5.50.35
28Ch RXDMAOVERRUNS Receive DMA Start-of-Frame and Middle-of-Frame Overruns Section 5.50.36
Register
94
C6472/TCI6486 EMAC/MDIO SPRUEF8F–March 2006–Revised November 2010
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