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MuxOneNAND2G(KFM2G16Q2A-DEBx)
- 106 -
FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
Program Operation Flow Diagram
NOTE :
1) DBS must be set before data input.
2) Data input could be done anywhere between "Start" and "Write Program Command".
3) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
During the execution of the Internal Program Routine, the host is not required to provide any further controls or timings. Furthermore, all com-
mands, except a Reset command, will be ignored. A reset during a program operation will cause data corruption at the corresponding location.
If a program error is detected at the completion of the Internal Program Routine, map out the block, including the page in error, and copy the
target data to another block. An error is signaled if DQ10 = "1" of Controller Status Register(F240h) .
Data input from the Host to the DataRAM can be done at any time during the Internal Program Routine after "Start" but before the "Write Pro-
gram Command" is written.
* DBS, DFS is for DDP
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Write ’Program’ Command
Add: F220h
DQ=0080h or 001Ah
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Write 0 to interrupt register
3)
Add: F241h DQ=0000h
Read Interrupt register
Add: F241h DQ[6]=WI
DQ[6]=1?
YES
Add: F240h DQ[10]=Error
Read Controller
Status Register
Program completed
DQ[10]=0?
YES
Program Error
NO
NO
Add: F240h DQ[14]=Lock
Read Controller
Status Register ‘Lock’ bit high
Program Lock Error
Start
Data Input
Write ’DFS*, FBA’ of Flash
Add: F100h DQ=DFS*’, FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Select DataRAM for DDP
1)
Add: F101h DQ=DBS*
Write Data into DataRAM
2)
ADD: DP DQ=Data-in
Completed?
NO
YES
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC