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MuxOneNAND2G(KFM2G16Q2A-DEBx)
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FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
Reset / Busy (RSTB)
This bit shows the Reset Operation status.
RSTB Information[7]
OTP Lock Status (OTP
L
)
This bit shows whether the OTP block is locked or unlocked. Locking the OTP has the effect of a 'write-protect' to guard against accidental re-
programming of data stored in the OTP block.
The OTP
L
status bit is automatically updated at power-on and it must be referred only on Chip1 within DDP.
OTP Lock Information[6]
1st Block OTP Lock Status (OTP
BL
)
This bit shows whether the 1st Block OTP is locked or unlocked.
Locking the 1st Block OTP has the effect of a 'Program/Erase protect' to guard against accidental re-programming of data stored in the 1st
block.
The OTP
BL
status bit is automatically updated at power-on and it must be referred only on Chip1 within DDP.
OTP Lock Information[5]
Plane1 Previous
This bit shows the previous program status of Plane1 at 2X Cache Program. This value is invalid only at the first ‘Read Controller Status Reg-
ister’ step of 2X Cache Program and 2X Interleave Cache Program operation. (Refer to 6.14 and 6.15)
Plane1 Previous Information[4]
Item Definition Description
RSTB Reset Operation Status
0 = ready (default)
1 = busy (see controller status output modes)
OTPL OTP Locked/Unlocked Status
0 OTP Block Unlock Status(Default)
1 OTP Block Lock Status(Disable OTP Program/Erase)
OTPBL 1st Block OTP Locked/Unlocked Status
0 1st Block OTP Unlock Status(Default)
1 1st Block OTPLock Status(Disable 1st Block OTP Program/Erase)
Plane1 Previous Status of previous program on Plane1
0Pass
1Fail