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MuxOneNAND2G(KFM2G16Q2A-DEBx)
- 168 -
FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
7.1.2 Polling the Interrupt Register Status Bit
An alternate method of determining the end of an operation is to continuously monitor the Interrupt Status Register Bit instead of using the INT
pin.
When using interrupt register instead of INT pin, INT pin is recommended to float to avoid power consumption at IOBE=0(disable).
This can be configured in either a synchronous mode or an asynchronous mode.
Synchronous Mode Using Interrupt Status Register Bit Polling
When operating synchronously, CE
, AVD, CLK, RDY, OE, and DQ pins on the host and MuxOneNAND are tied together.
RDY could be connected as one of following guides.
Asynchronous Mode Using Interrupt Status Register Bit Polling
When configured to operate in an asynchronous mode, CE
, AVD, OE and DQ of the MuxOneNAND are tied to corresponding pins of the Host.
CLK is tied to the Host Vss (Ground). RDY is NOT connected.
INT
Command
Host MuxOneNAND
RDY(WAIT)
OE
CLK
CE
RDY
OE
CLK
CE
AVD
DQ DQ
Host MuxOneNAND
OE
CLK
CE
RDY
OE
CLK
CE
AVD
DQ DQ
Handshaking Mode Non-Handshaking Mode
AVD
AVD
Host MuxOneNAND
OE
CE
RDY
OE
CLK
CE
AVD
DQ DQ
Vss
AVD