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MuxOneNAND2G(KFM2G16Q2A-DEBx)
- 98 -
FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
Cache Read Diagram
INT
A/DQ0:
A/DQ15
1st
Address
Host reads 1st
data from DataRAM
Setting
2nd
Address
Setting
Command
Setting
3rd
Address
Setting
1)
4th
Address
Setting
Command
Setting
Status
Read
Status
Read
Host reads (n-2)th
data from DataRAM
Command
Setting
Status
Read
Host reads (n-1)th
data from DataRAM
Command
Setting
Status
Read
Finish
Host reads nth
data from DataRAM
-1st Address Setting : Address Setting Operation for first page load(FCBA, FCPA, FCSA, and BSA).
-2nd~nth Address Setting : Address Setting Operation from 2nd~nth page load(FBA and FPA).
-Command Setting : It consists of writing 0 to Interrupt register and writing command to Command register.
(In INT auto mode, writing 0 to Interrupt register may be ignored)
-Status Read : It consists of INT high state checking and Controller Status Register checking step.
-Host read 1st~nth data from DataRAM : During this step, Host can read data from DataRAM by any read mode which supported by MuxOneNAND.
-Finish Command Setting : If host want to finish Cache Read, Host can finish Cache Read by issuing Finish Command.
-Controller Status Register Status: During Cache Read - Ongoing / Load
ECC Error during Cache Read - Ongoing / Load / Error
ECC Error at Finish Cache Read - Load / Error
NOTE :
1) 3rd~nth address can be set during INT=low, and also during INT=High, before next ‘Cache Read Command’.
INT
A/DQ0:
A/DQ15
(cont.)
(cont.)