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MuxOneNAND2G(KFM2G16Q2A-DEBx)
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FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
Cache Read Flow Chart
NOTE :
1) In case of first cycle cache read, BSA must be set to 1000 or 1100, and from second cycle cache read,
BSA will automatically be switched between DataRAM0 and DataRAM1.
2) BSC, FSA and FCSA must be set to "00".
3) These steps can also be set during INT=High, before next ’Cache Read Command’.
4) ’Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.1
5) When host reads data from DataRAM, host should start from the DataRAM of the first set BSA, and then next DataRAM alternately, as the number of Cache
Read.
Start
Write ‘BSA
1)
, BSC
2)
’ of Flash
Add: F200h DQ=BSA, BSC
Write ‘FPA, FSA
2)
’ of Flash
Add: F107h DQ=FPA, FSA
Write ‘Cache Read’ Command
Add: F220h DQ=000Eh
Map out
Write 0 to Interrupt register
4)
Add: F241h DQ=0000h
Write ‘FPA, FSA
2)
’ of Flash
3)
Add: F107h DQ=FPA, FSA
END
Add: F220h DQ=000Ch
Host reads data from
DataRAM
6)
Wait for INT high State
Add: F241h DQ[15]=INT
Read Controller Status
Add: F240h DQ[10]=Error
Register
DQ[10]=0?
Yes
No
Host reads data from
DataRAM
Write ‘Finish Cache Read
Command’ @ Final Read
Write ’DFS*, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Write ’DFS*, FBA’ of Flash
3)
Add: F100h DQ=DFS, FBA
Read Controller Status
DQ[15]=Ongo & DQ[13]=Load
Register Add: F240h
DQ[15]=1 & DQ[13]=1 ?
Yes
No
Wait for INT high State
Add: F241h DQ[15]=INT
Read Controller Status
Add: F240h DQ[10]=Error
Register
DQ[10]=0?
Yes
Write 0 to Interrupt register
4)
Add: F241h DQ=0000h
Host reads data from
DataRAM
5)
No
Done with
No
Yes
(n-1)th command
Write ‘Cache Read’ Command
Add: F220h DQ=000Eh
Wait for INT high State
Add: F241h DQ[15]=INT
Read Controller Status
Add: F240h DQ[10]=Error
Register
DQ[10]=0?
Yes
Write 0 to Interrupt register
4)
Add: F241h DQ=0000h
No
Select DataRAM for DDP
3)
Add: F101h DQ=DBS
* DBS, DFS is for DDP
(DFS must be same)
Write ‘FCBA’ of Flash
Add: F102h DQ=FCBA
Write ‘FCPA, FCSA
2)
’ of Flash
Add: F103h DQ=FCPA, FCSA
issue?