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MuxOneNAND2G(KFM2G16Q2A-DEBx)
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6.15 2X Interleave Cache Program Operation Timing
1st data input 2nd data input
Address Setting
2X cache program Command
ADQ0~
A1, A2, A3 : Address of DataRAM to be written.
INT: Indicator for DataRAM’s Status (Ready=High, Busy=Low)
Ongoing Status : Indicated by OnGo bit in Controller Status Register [15] (F240h)
4KB data input : Asynch Write / Synch Write available.
Command input and INT bit or pin behavior is based on ‘INT auto mode’.
NOTE :
1) INT pin might toggle when INT bit of chip1 turns to ready before host issues ‘2X program’ command on chip2.
ADQ15
A1 A2
High-Z
INT bit
....
..
4KB data into
2 DataRAMs
4KB data into
2 DataRAMs
2X Cache program Command
2X program Command
Last data input
An
4KB data into
2 DataRAMs
...
Ongoing
Status
Controller Status Register Check
Plane1 / Plane2 current : Invalid
Plane1 / Plane2 previous: Pass=0, Fail=1
Controller Status Register Check
Plane1 / Plane2 current : Pass=0, Fail=1
Plane1 / Plane2 previous: Pass=0, Fail=1
...
1st data input 2nd data input
Address Setting
2X cache program Command
ADQ0~
ADQ15
A1
A2
...
..
4KB data into
2 DataRAMs
4KB data into
2 DataRAMs
2X Cache program Command
2X program Command
Last data input
An
4KB data into
2 DataRAMs
...
Ongoing
Status
Controller Status Register Check
Plane1 / Plane2 current : Invalid
Plane1 / Plane2 previous: Pass=0, Fail=1
Controller Status Register Check
Plane1 / Plane2 current : Pass=0, Fail=1
Plane1 / Plane2 previous: Pass=0, Fail=
1
...
Chip1
Chip2
.....
.....
.....
Controller Status Register Check
Plane1 / Plane2 current : Invalid (Fixed to 0)
Plane1 / Plane2 previous: Invalid (Fixed to 0)
Controller Status Register Check
Plane1 / Plane2 current : Invalid (Fixed to 0)
Plane1 / Plane2 previous: Invalid (Fixed to 0)
INT bit
INT Pin
...
1)