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MuxOneNAND2G(KFM2G16Q2A-DEBx)
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FLASH MEMORY
MuxOneNAND4G(KFN4G16Q2A-DEBx)
3.13.3 Multi-Block Erase Verify Read Operation
After a Multi-Block Erase Operation, verify Erase Operation result of each block with Multi-Block Erase Verify Command combined with
address of each block.
If a failed address is identified, it must be managed by firmware.
Multi Block Erase/ Multi Block Erase Verify Read Flow Chart
NOTE :
1) DFS should be a fixed value, for Multi Block Erase is performed within a single chip.
2) ‘Write 0 to interrupt register’ step may be ignored when using INT auto mode. Refer to chapter 2.8.18.
Add: F240h DQ[10]=0
Read Controller
Status Register
Start
Write ‘Multi Block Erase’
Add: F220h DQ=0095h
Wait for INT register
Add: F241h DQ[15]=INT
Final Multi Block
YES
NO
low to high transition
Write 0 to interrupt register
Add: F241h DQ=0000h
Command
Erase?
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Write ‘Block Erase
Add: F220h DQ=0094h
Wait for INT register
Add: F241h DQ[15]=INT
low to high transition
Write 0 to interrupt register
2)
Add: F241h DQ=0000h
Command’
Multi Block Erase Verify Read
Write ‘DFS, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Write ‘Multi Block Erase
Add: F220h DQ=0071h
Wait for INT register
Add: F241h DQ=[15]=INT
low to high transition
Write 0 to interrupt register
Add: F241h DQ=0000h
Verify Read Command’
Read Controller
Add: F240h DQ[10]=Error
Status Register
DQ[10]=0?
Multi Block Erase completed
Final Multi Block
YES
NO
Erase Address?
Erase completed
YES
Erase Error
NO
*DBS, DFS is for DDP
Select DataRAM for DDP
Add: F101h DQ=DBS*
Read Interrupt register
Add: F241h DQ[5]=EI
DQ[5]=1?
YES
Add: F240h DQ[14]=Lock
Read Controller
Status Register ‘Lock’ bit high
Multi block Erase Lock/
NO
Erase Lock Error
NO
Read Interrupt register
Add: F241h DQ[5]=EI
DQ[5]=1?
YES
Add: F240h DQ[10]=0
Read Controller
Status Register
(DFS must be same)
Write ‘DFS
1)
, FBA’ of Flash
Add: F100h DQ=DFS, FBA